1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to a multi-mode scheduler for clock tree synthesis (CTS) to achieve high-quality skew-balanced clock trees across multiple modes.
2. Related Art
Advances in process technology and a practically unlimited appetite for consumer electronics have fueled a rapid increase in the size and complexity of integrated circuit (IC) designs. The goal of clock tree synthesis is to convert a high-level description of a clock tree into an implementation that meets a set of constraints (e.g., clock skew constraints, area constraints, power constraints, routing constraints, placement constraints, etc.). Today's IC designs typically have multiple modes for operation (e.g., functional mode and test mode), and each mode typically has its own clock. Due to the rapidly increasing size and complexity of IC designs, and also because IC designs have multiple modes, it is becoming increasingly difficult to create high quality clock trees for IC designs, especially to meet skew balancing constraints across all modes.